Gigahertz FPGAs with new architectural ideas

The demand for high speed Field Programmable Gate Arrays (FPGAs) has always been on a rise. This was never possible using CMOS as the basic device. People were able to achieve frequencies in the range of 10-220 MHz using CMOS. The availability of SiGe HBT devices has opened the door for Gigahertz FPGAs. Speeds over 5 GHz were reported by B. S. Goda and Channakeshav et al. using SiGe 5HP technology. Using IBM's new 7HP technology, SiGe HBT devices with cutoff frequencies (f/sub T/) over 100 GHz can be fabricated. Apart from the improvement in device speed, architectural changes have been made to improve the speed and reduce the power. This paper is mainly going to elaborate on the architecture of the new SiGe FPGA and its advantages over the previous generation SiGe FPGA. The entire Configurable Logic Block (CLB) has been implemented using 3 Current Mode Logic (CML) trees. The power consumption of the redesigned CLB is "5.04 mW - sequential, 3.36 mW - combinational" and the maximum operating frequency of the new logic cell is 11.7 GHz. Apart from these, 2 memory planes have been added to change the personality of the FPGA dynamically. The original Widlar current mirror has been replaced by a CMOS current mirror which avoids the loading effect.