Comparison of multiple-gate MOSFET architectures using Monte Carlo simulation

Multiple-gate SOI MOSFETs with gate length equal to 25 nm are compared using device Monte Carlo simulation. In such architectures, the short channel effects may be controlled with much less stringent body and oxide thickness requirements than in single-gate MOSFET. Our results highlight that planar double-gate MOSFET is a good candidate to obtain high current drive per unit-width and low subthreshold leakage with aggressive delay time. Additionally, this device offers much better ability to high integration density than nonplanar devices as triple-gate or quadruple-gate MOSFETs. However, we show that source-drain regions have to be carefully scaled to optimize the trade off between access resistance and fringe capacitance.