Bias temperature instability in scaled CMOS technologies: A circuit perspective

Abstract Bias temperature instability has impacted scaling of conventional poly-Si/SiON CMOS technologies and remains a critical device reliability mechanism for metal gate/high-k stacks in planar and FinFET device architecture. The material and modeling aspects have been extensively studied using discrete MOSFETs and more recently expanded to CMOS circuits to demonstrate its impact on digital circuit aging. In this paper we summarize our understanding of the BTI mechanism in scaled CMOS technologies and discuss the correlation between discrete device degradation and circuit/SRAM aging.