Beyond 320 Mbyte/s with 2eSST and Bus Invert coding on VME64x

The VME64x standard includes a double data rate block transfer cycle known as 2eSST. In order to achieve the maximum bandwidth, 64-bit words are exchanged in bursts across the backplane without handshake between master and slave. Data is clocked by both the falling and rising edges of a single strobe line driven by the data producer. Transfer rates up to 320 Byte/s are presently supported: the standard also foresees even faster speed grades, to be released in the future. In this paper we present our tests on 2eSST beyond the actual limit set by the protocol. Bit error rate (BER), data timing jitter and eye-diagrams have been measured for selected bus layouts and data patterns. Performance achieved with and without the bus-invert encoding of the transmitted payloads are compared. Our results show that on a 21 slot VME64x backplane reliable transfers can be sustained with selected loads up to 800 MByte/s with a 10 -12 BER.