10Gb/s receiver with track-and-hold-type linear phase detector and charge-redistribution 1 st -order ΔΣ modulator

A CDR circuit and a phase detector are the key building blocks of high-speed interconnect systems. Today, most CDR circuits use bang-bang phase detectors. These phse detectors have several advantages, including low power consumption, a simple circuit structure, and compatibility with digital circuits [1,2]. However, bang-bang phase detectors have the intrinsic drawback of large quantization noise. Therefore, the CDR loop bandwidth must be relatively low to mitigate the effect of the quantization noise by time averaging. In particular, digital CDRs operated in a Δ-modulation loop are susceptible to quantization noise. On the other hand, linear phase detectors (LPDs) do not exhibit quantization noise and therefore by using them one can potentially increase the CDR bandwidth to achieve improved jitter tolerance. However, conventional LPDs, such as the Hogge phase detector, which detect the phase difference as a pulse width, cannot be easily incorporated in a digital CDR [3]. In this paper, a 10Gb/s receiver is described that is equipped with a track-and-hold-type LPD as well as a charge-redistribution ΔΣ modulator for incorporation in a digital CDR. The 10Gb/s receiver exhibited low quantization errors and high loop bandwidth that are due to the use of a linear phase detector while it maintains the advantages of a digital CDR circuit, such as low power consumption, small area occupation, fast locking time, and a low-jitter recovered clock because an internal VCO is not needed. The tracking bandwidth of the CDR circuit is about 20MHz, and the power consumption of the receiver is 65mW