Variation-immune resistive Non-Volatile Memory using self-organized sub-bank circuit designs

While technology scaling enables increased density for memory cells, the intrinsic high leakage power of CMOS technology and the demand for reduced energy consumption inspires the use of emerging technology alternatives as Non-Volatile Memory (NVM) including STT-MRAM, PCM, and RRAM. However, their narrow resistive sensing margins exacerbate the impact of Process Variations (PV) in high-density NVM arrays, including on-chip cache and primary memory. Large-latency and power-hungry Sense Amplifiers (SAs) have been adapted to combat PV in the past. Herein, we propose a novel approach to actually leverage the PV in NVM arrays using Self-Organized Sub-bank (SOS) design. SOS engages the preferred SA alternative based on the intrinsic as-built behavior of the resistive sensing timing margin to reduce the latency and power consumption while maintaining acceptable access time. Our experimental results indicate that the PV effect in our case study may perturb around 27.5% of the data sensing operations from which 21.5% are classified as extremely vulnerable. SOS alleviates the sensing vulnerability by 40% on average to reduce the risk of application's contamination by fault propagation. Additionally, new categories of resistive read sensing dependability are defined for broad adaption.