Low-power reference buffer for successive approximation register analog-to-digital converters

This paper analyzes the performance of amplification stages when they are used to buffer reference voltages. This topic is particularly interesting for Successive Approximation Register Analog to Digital Converters (SAR-ADCs) whose efficiency was tremendously pushed down during last years. A conventional solution for a reference buffer including a closed loop single stage opamp is firstly presented in order to individuate its limits. The conventional solution is used as benchmark for the proposed buffer circuit solution. It includes a reconfigurable circuit made by a charge pump, which enables a rapid charge of the output capacitive load. After the charging phase, the circuit is commutated into a closed loop opamp to let the feedback take the control of the output voltage. Both circuits were designed in CMOS 28nm technology with 1V supply. The proposed circuit has about half of the power consumption of the conventional one, 398μW and 774μW respectively, considering the same settling error.