Total-dose radiation tolerance of a commercial 0.35 /spl mu/m CMOS process

We have measured the properties of test structures from two different lots fabricated at Hewlett-Packard on their 0.35 /spl mu/m CMOS process after exposure to total ionizing radiation. The threshold voltage shifts associated with the gate oxide were shown to be small, consistent with the presence of a thin gate oxide. Measurements on various ring oscillators indicated no change in gate delay or power with exposure to radiation, consistent with minimal shifts in transistor threshold voltages. A discrepancy was observed between the two lots for NMOS minimal geometry transistors. Transistors from the earlier lot showed no additional off-state leakage, even at a total ionizing dose (TID) of 300 krad, while transistors from the more recent lot showed up to 1 /spl mu/A leakage at 300 krad. Measurements of field-oxide transistors from the first lot indicated the p-substrate did not invert at doses up to 300 krad. Unfortunately, the field oxide transistors from the second lot were not functional. The observed discrepancies between the two lots will require further measurements on future lots.