N-channel Junction-less Vertical Slit Field-Effect Transistor (VeSFET): Fabrication-based Feasibility Assessment

The silicon implementation of junction-less Vertical Slit Field-Effect Transistor (VeSFET) fabricated on SOI wafer using conventional CMOS processes is presented. The twin poly-Si gates on the side walls of the vertical slit are defined using damascene process making them self-aligned and free from lithography restrictions on tall features. The NMOS transistors fabricated on 42 nm wide and 117 nm tall slit showed excellent electrical characteristics: ION = 20µA, ION/IOFF ratio = 10 9 , SS = 62mV/dec, DIBL = 13mV/V. The second gate could be used for providing better electrostatic control, threshold voltage tuning, or additional functionality.