Characterization of the mechanisms of charge Trapping in GaN Vertical devices

In this master thesis a new type of transistor is analyzed: the GaN Vertical Fin FET Transistor. This kind of transistor is made on GaN, a wide bandgap semiconductor which is a promising material for the future power electronics . Fin FET Transistor is based on a fin-architecture and the current flows vertically through a GaN made nanometer-sized channel having a MOS stack on the sides. In this work different measurements are performed in order to see the variation of the threshold voltage and channel resistance of the transistor varying the fin width and external parameters such as temperature and exposure to UV-light. Oxide trapping phenomena are analysed by applying to the gate an increasing positive bias potential and for increasing periods of time. Simulations are performed in order to further analyze the results and give an extensive explanation of the charge trapping behaviour in different bias conditions.