Challenges for giga-scale integration

Abstract The “giga-chip era” has begun. A new challenging approach to ULSI reliability is now greatly needed in response to the “paradigm shift” now being brought about by simple scaling limitations, increased process complexity, and diversified ULSI application to advanced multimedia and personal digital assistant (PDA) systems. A good example of this shift is the new movement from simple failure analysis by sampling the output of a manufacturing line to the “building-in-reliability” approach. To pursue this technique, greater importance will be attached to a deeper physical understanding of the significant relationships between the input variables and product reliability (including frequent use of Computer Aided Design, CAD and Design Automation, DA), and to total concurrent engineering from research labs to production sites. Furthermore, fast, new ULSI testing methods and new yield-enhancing redundancy techniques that reduce costs will be increasingly needed to achieve high reliability for ULSIs with 10 9 devices on a single chip. Only with these approaches can we pave the way for giga-scale integration (GSI) in the 21st century.