OPC strategies to minimize mask cost and writing time

As k1 factors decline, optical proximity correction (OPC) treatments required to maintain dimensional tolerances involve increasingly complex correction shapes. This translates to more detailed, larger mask pattern databases. Intricate, dense mask-layouts increase mask writing time and cost. OPC employment within a growing number of lithography layers compounds the issue, leading to skyrocketing mask-set costs and long turn-times. ASIC manufacturing, where average chip life cycles consume less than 500 wafers, is particularly hard hit by elevated mask manufacturing costs. OPC increases mask data mainly by adding geometric detail - serifs, hammerheads, jogs, etc - to the design layout. The vertex count, a measure of shape complexity, typically expands by a factor of 2 to 5, depending on OPC objectives and accuracy requirements. OPC can also increase hierarchic data file size through loss of hierarchic compression. In this paper we outline several alternatives for reducing OPC data base size and for making OPC layout configurations friendlier to mask fabrication tools. An underlying assumption is that there is an optimum OPC treatment dictated by the behavior of the process, and that approximations to this ideal involve trade-offs with OPC accuracy. To whatever extent OPC effectiveness can be maintained while accuracy is compromised, mask complexity can be reduced.