A 2GS/s 8b time-interleaved SAR ADC for millimeter-wave pulsed radar baseband SoC

This paper presents a 2 GS/s 8-bit 16× time-interleaved (TI) ADC for millimeter-wave pulsed radar baseband SoC in 40nm CMOS. An extremely-compact foreground timing calibration suppresses sampling clock skews among sub-ADCs within 400fs. Measured SFDR and SNDR at 1GHz full-Nyquist is therefore enhanced by 16dB and 11dB, respectively. Unlike conventional calibration based on redundant ADCs or DSP-assisted calculations, just a few small resistors and a capacitor are needed, resulting in only 0.4% area penalty. This area saving enables the compact integration of the radar SoC with beamforming where 8-channel TI-ADCs occupy the dominant chip area otherwise. Even though this is foreground, no system performance is sacrificed because the calibration sequence is closed-loop and fast enough to be executed during an existing calibration interval in a periodic beam transmission sequence. Thanks to the foreground scheme, the TI-ADC including the input buffer consumes only 54.2mW and 355fJ/step.