Analysis of Hot Carrier Degradation of Lateral Double-Diffused Metal–Oxide–Semiconductor under Gate Pulse Stress

The lateral double-diffused metal–oxide–semiconductor (LDMOS) transistor is one of the key elements of high-power devices. It is difficult to evaluate the degradation of an LDMOS at the required temperature range, because the self-heating effect of an LDMOS is too large for conventional evaluation in DC. In this paper, we report on the hot carrier degradation of an LDMOS under high-power operation, by investigating the LDMOS deterioration in the case that both the device structure and junction temperature (Tj) are different. The Tj of an LDMOS is controlled by operating the gate voltage (Vg) in pulse mode. Controlling Tj by operating Vg in pulse mode, the Tj dependence of hot carrier degradation under high-power operation can be evaluated widely and quantitatively. The threshold voltage (Vth) shift is observed according to the bias temperature mode irrespective of the device structure. On the other hand, the shift of drain current is affected by the length of the accumulation region under the gate electrode, and a relatively small increase in drain current (Ids) shift is observed with decreasing Tj. These phenomena are clarified from the results of charge pumping measurement and simulation.