An novel FDWT and IDWT architecture for JPEG2000

A novel forward and inverse discrete wavelet transformation VLSI architecture for JPEG2000 is proposed. First of all, the reducing scaling coefficients multiplication algorithm (RSCM) was introduced. Then, starting from transform characteristics, the architecture is presented showing both performance and cost. Our implementation is a new architecture that can perform both FDWT and IDWT using filters recommended by JPEG2000. Our architecture has a flexible configuration and high processing speed. The architecture has been implemented in RTL-level Verilog. The estimated number of gates in our proposed architecture in SIMC 0.18-/spl mu/m technology is 15500 and the estimated frequency of operation is 150 MHz.