A pipelined all-digital delta-sigma modulator for fractional-N frequency synthesis

In this paper, we present the design considerations and implementation aspects of a pipelined all-digital fourth-order Multi-Stage-Noise-Shaping (MASH) Delta-Sigma (/spl Delta//spl Sigma/) modulator suitable for Fractional-N (F-N) Phase Locked Loop (PLL) frequency synthesis applications. The modulator has successfully been targeted to an Altera/sup TM/ Field-Programmable-Gate-Array (FPGA) device. The functional operation of the modulator has been verified through structural bit-level simulations as well as experimental results on the actual FPGA implementation.