Selective GeO x -scavenging from interfacial layer on Si 1−x Ge x channel for high mobility Si/Si 1−x Ge x CMOS application

We demonstrate a technique for selective GeO x -scavenging which creates a GeO x -free IL on Si 1−x Ge x substrates. This process reduces N it by >60% to 2e11 and increases high-field mobility at N inv =1e13 cm −2 by ∼1.3× in Si 0.6 Ge 0.4 pFETs with sub-nm EOT.