Decoding circuit and a display device
2006
In each of sub-decoding circuits at a first stage provided for a plurality of output candidates arranged adjacently, for selecting corresponding output candidates in accordance with a bit of multibit data for transmission to subsequent stage sub-decoding circuits, unit decoders are arranged in parallel in a direction perpendicular to an arranging direction of the output candidates. A size in a vertical direction along which reference voltages of the output candidates of a decoding circuit are arranged can be reduced without increasing a size in a horizontal direction.
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