Source synchronization and timing Vernier techniques for 1.2 GB/s SLDRAM interface

This paper describes a validation system for an SLDRAM interface. The SLDRAM system utilizes two techniques to achieve a high data-transfer rate with a conventional module mounting style. The first technique is a source-synchronization scheme. Since the chip that transmits data also supplies the data clock, the clock and data are completely synchronous. The second is the timing vernier technique. A wait time for output data is programmable in each SLDRAM. Therefore, the time at which data arrive at the controller from any SLDRAM can be set by the controller with a 200-ps step size. The validation chip is designed to emulate these operations. The chip is fabricated using a 0.35-/spl mu/m CMOS process technology and packaged in a conventional 0.65-mm pitch thin small out-line package, mounted on a single-chip module, and put into an eight-module system. A stub series terminated logic (SSTL)-like interface is adopted for high-speed signals. From system-level measurements, the data eye width of 600 ps is obtained at a data rate of 600 Mbps. Errorless data transmission is observed in both read and write operations in a bit-error rate testing. The validation system has successfully demonstrated a data-transmission rate of 1.2 GB/s (600 Mbit/s/pin) using source-synchronization and timing vernier techniques at the supply voltage of 2.5 V.