The challenges and limitations on triple level cell geometry and process beyond 20 nm NAND Flash technology

Yunbong Lee,Byoungjun Park,DaeHwan Yun,YeonJoo Jeong,Pyoung Hwa Kim,Ji Yul Park,Hae chang Yang,Myoung Kwan Cho,Kun Ok Ahn,Yo-Hwan Koh

The challenges and limitations on triple level cell geometry and process beyond 20 nm NAND Flash technology

2010

Yunbong Lee
Byoungjun Park
DaeHwan Yun
YeonJoo Jeong
Pyoung Hwa Kim
Ji Yul Park
Hae chang Yang
Myoung Kwan Cho
Kun Ok Ahn
Yo-Hwan Koh

This paper investigates the challenges and difficulties of TLC cell geometry and process beyond 20nm NAND technology from the viewpoint of programmed V th level, new HCI disturbance and charge loss in the highest programmed level.

Keywords:

Electronic engineering
Logic gate
Geometry
NAND gate
Computer science
Hot-carrier injection
Flash memory
triple level cell
charge loss
cell geometry

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