Performance Optimization of BiCMOS Circuits under Reduced Supply Voltage

As the supply voltage is reduced, the speed superiority of BiCMOS over CMOS may be diminished, but BiCMOS still has the advantage of inducing relatively smaller characteristic degradation in nMOS transistors by suppressing the drain voltage in the gate. Introducing a new quantitative methodology to evaluate hot electron-induced degradation of nMOS transistor characteristics, this report finds that both BiNMOS gates and CBiMOS gates will have a considerable superiority over CMOS gates in the voltage range from 2.5 V to 3.3 V, even with the same nMOS transistor characteristics. BiNMOS is 30% faster than CMOS owing to amplification of the pMOS drain current by an npn transistor. CBiCMOS is 40% faster and has a sevenfold longer life than CMOS. The speed improvement comes from amplification of both pMOS and nMOS drain currents by npn and pnp transistors, respectively, and the lifetime improvement is due to the effect of the voltage drop through the pnp transistors on the drain terminal of the nMOS transistors. The analytical methodology was also utilized to choose an optimum drain structure, although CMOS necessitates the LDD (lightly doped drain), SD (single drain) structure. Thus, the speed of the gates can be further improved, and the speed of CBiCMOS is expected to be 45% faster than that of CMOS gates. Even in the case of SD structure, the lifetime of CBiCMOS was estimated to be two orders of magnitude longer than that of CMOS with LDD structure. © 1998 Scripta Technica. Electr Eng Jpn, 121(4): 56–64, 1997