The clock recovery circuit and a communication device

The invention provides a clock recovery circuit. The clock recovery circuit comprises a phase discriminator, a loop filter, a phase scanner and a digital voltage control oscillator, wherein the phase discriminator is used for detecting phase error of an input decision signal and a decision error signal so as to obtain a phase error value, wherein the decision signal is an estimated value of a digital signal obtained by processing the signal sent by the opposite end; the decision error signal represents the error between the digital signal and the estimated value; the loop filter is used for filtering a high-frequency part of the phase error value to obtain a low-frequency phase error value; the phase scanner is used for generating a pulse signal according to a control signal and a data signal; the digital voltage control oscillator is used for operating according to the low-frequency phase error value and the pulse signal to obtain a phase regulating signal, wherein the phase regulating signal is used for driving a phase selector to select the phase for a local clock, so as to recover a clock signal as requirement. Compared with the clock recovery circuit in the prior art, the clock recovery circuit has the advantages of being capable of quickly converging and quickly synchronizing a clock.