A High Throughput Hardware Solution for the H.264/AVC Quarter-Pixel Motion Estimation Refinement

This work proposes a hardware solution for the H.264/AVC Quarter-Pixel Motion Estimation Refinement, ready to be used in a complete Fractional Motion Estimation architecture. The architecture was optimized to reach a high throughput through a balanced pipeline and parallelism exploration. The design was described in VHDL and synthesized to an Altera Stratix III FPGA device, achieving an operation frequency of 245 MHz and processing up to 39 QHDTV frames (3840x2048 pixels) per second. This architecture is also able to reach real time when processing lower resolutions, like HD 1080p (1920x1080 pixels) with lower operation frequencies. The final results are very competitive when compared to related works.