Engineering a Robust 2" Wafer HTS Process for IC Applications using Taguchi Methods

The authors report on the advancement in fabrication of high temperature superconducting (HTS) integrated circuit elements including junctions, crossovers of superconducting interconnects and layer-to-layer superconducting vias in a multilayer process. Experiments were performed using Taguchi methods to examine and compare critical factors in these circuit elements. Factors include angle of HTS deposition by pulsed laser deposition (PLD), pre-cleaning and annealing dwell time prior to epitaxial depositions and angle of film edges created by ion milling. Improvements of 100 times in crossover critical current, 16 times in via critical current and reduction of junction excess current by a factor of 2 were accomplished by this approach and confirmed by subsequent wafer fabrications. Integration of these processes into a two-inch wafer process allows use of automated stepping equipment with deep sub-micron layer-to-layer alignment capability. Improved layer-to- layer alignment enables designs with reduced parasitic inductance, which in turn allows greater process margin for the ultimate goal of building superconducting digital circuitry.