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High‐speed sense circuit techniques for a 1‐mbit BiCMOS cache SRAM
High‐speed sense circuit techniques for a 1‐mbit BiCMOS cache SRAM
1998
Akihiko Emori
Kunihiko Suzuki
Seigoh Yukutake
Sadayuki Ookuma
Kinya Mitumoto
Takashi Akioka
Masahiro Iwamura
Noboru Akiyama
Keywords:
Megabit
Computer science
BiCMOS
Electronic engineering
Sense amplifier
Embedded system
Static random-access memory
Cache
CPU cache
Correction
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