Efficient hardware usage in the mask tapeout flow

With each new technology node there is an increase in the number of layers requiring Optical Proximity Correction (OPC) and verification. This increases the time spent on the mask tapeout flow which is already a lengthy portion of the production flow. New technology nodes not only have additional layers that require OPC but most critical layers also end up with more complex OPC requirements relative to previous generations slowing the tapeout flow even further. In an effort to maintain acceptable turnaround time (TAT) more hardware resources are added at each node and electronic design automation (EDA) suppliers are pushed to improve the software performance. The more we can parallelize operations within the tapeout flow the more efficient we can be with the use of the CPU resources and drive down the overall TAT. Traditional flows go through several cycles where data is broken up into templates, the templates are distributed to compute farms for processing, pieced back together, and sometimes written to disk before starting the next operation in the tapeout flow. During each of these cycles there are ramp up, ramp down, and input/output (I/O) times that are incurred affecting the efficient use of hardware resources. This paper will explore the advantages of pipelining the templates from one operation to the next in order to minimize these effects.