Interconnect-aware device targeting from PPA perspective

CMOS scaling so far enabled simultaneous system throughput scaling by concurrent improvements in delay, power, and area with thanks to Moore's law. CMOS scaling becomes more difficult with the limits of interconnect and increasing wafer cost. It is empirical to consider the system-on-chip (SoC) context to choose the most critical process knobs since most of processing budget to scale a technology node is already consumed by increasing process steps due to multiple patterning. In this paper we will show that the device parasitics and the interconnect resistance are the most critical performance scaling barriers for technology nodes beyond 7 nm (N7). We will demonstrate the impact of process and design knobs enabling performance and power improvements for the N7 node as defined in ITRS 2015 edition while still continuing to scale the area to limit the cost.