High-speed sensing scheme for CMOS DRAMs

A significant improvement in sensing speed over the half-V/sub DD/ bit-line precharge sensing scheme is obtained by precharging the bit line to approximately 2/3 V/sub DD/. The 2/3-V/sub DD/ sensing scheme also results in higher-bit-line capacitance, asymmetrical bit-line swing, and higher power consumption. However, the speed advantage of 2/3-V/sub DD/ sensing may outweigh the disadvantages and can significantly improve DRAM performance. For the unboosted word-line case, symmetrical bit-line swing can be retained by limiting the bit-line downward voltage swing through a clamping circuit added to the sense amplifier, resulting in almost no loss of stored charge in a cell. The authors show that the 2/3-V/sub DD/ sensing with a limited bit-line swing has several distinct advantages over the half-V/sub DD/ sensing scheme and is particularly suitable for high-performance high density CMOS DRAMs. >