Control of etch and deposition for embedded SiGe

Embedded SiGe is applied in CMOS at recent technology nodes to improve device performance and enable scaling. The position of the SiGe surface with respect to the channel is found to have significant impact on the pFET threshold voltage and also on device variability. Therefore the recess etch and deposition of the embedded SiGe has to be very well controlled. We show the sensitivity of the device to the fill process and describe the feed forward and feedback techniques used to optimize the control of epitaxy.