Large-scale complementary macroelectronics using hybrid integration of carbon nanotubes and IGZO thin-film transistors

A method of fabricating a logic element, the method includes forming a p-type nanomaterial thin film transistor on a substrate, forming a n-type metal oxide thin film transistor on the substrate, and connecting the p-type nanomaterial thin film transistor to the n-type metal oxide thin film transistor to form the logic element. The logic element is a hybrid complementary logic element.