Designing of Parity Preserving Reversible Vedic Multiplier

Reversible logic is used in designing low-power CMOS circuits, optical information processing, and quantum computing. Moreover, using parity preserving gates in reversible circuits provides additional reliability in error detection. In this paper, a new parity preserving reversible block is presented. Also a 2 × 2 parity preserving reversible Vedic multiplier circuit is proposed. Then a 4 × 4 parity preserving reversible Vedic multiplier is presented. Afterward, a reversible Vedic multiplier in n × n dimensions is presented. In fact, a circuit in various dimensions is presented in this section. Finally, a computational relation for the proposed circuit is obtained to calculate the quantum cost of the circuit in desired dimensions. The proposed reversible multiplier circuits are evaluated in 2 × 2 and 4 × 4 dimensions compared to existing reversible logic-based multiplier circuits. The quantum costs, the number of constant inputs and the number of garbage outputs are significantly decreased in the suggested reversible multiplier circuits.