Fault-Aware ECC Techniques for Reliability Enhancement of Flash Memory

Due to the rapid process scaling trend and reduced cell size, flash memory faces more and more challenges in reliability and endurance. This dilemma becomes more critical in multilevel flash memory due to the tight spacing between adjacent programmed levels. Error correction codes with stronger protection capability are usually adopted to all flash pages as a solution. However, the growth of raw bit error rate (RBER) induced by increasing P/E cycles will lead to uneven distribution of errors. Applying uniform ECC protection capability for all flash pages might incur unnecessary hardware overhead and latency. In this paper, fault-aware error correction code (PECC) techniques are proposed to cure these drawbacks of uniform protection. The main idea is to upgrade the ECC protection levels for flash pages when their correction slack is below the specified threshold. An ECC SRAM and an ECC CAM are used for storing extra check bits and accessing purposes. According to experimental results, we can enhance the reliability of flash memories with negligible hardware cost.