Channel BER Measurement for a 5.8Gb/s/pin unidirectional differential I/O for DRAM application

A 5.8 Gb/s/pin DRAM with unidirectional differential I/Os and 1 Gbit memory core was designed and 23.2 GB/s memory module was assembled. Tx BER measurement on an electrical test board similar to real memory sub-systempsilas environment was performed and the results show that no additional coding for the differential I/O protection, like CRC, seems to be required up to 5.8 Gb/s/pin operation. Also, an efficient timing usage method using matched path for a possible implementation of CRC computation in ODIC architecture was proposed.