An All Digital Distributed Sensor Network Based Framework for Continuous Noise Monitoring and Timing Failure Analysis in SoCs

Increased functional density with shrinking technology could result in escalating noise-induced failures in the field. Further, the low correlation between system level functional test and production test is making it difficult to better screen parts that would fail in the field due to noise. To address these issues, in this paper we present a light-weight fully digital on-chip distributed sensor network to continuously monitor the noise profile and generate a trace for diagnosis of any noise-induced failure at silicon validation, structural test, and system test phases of SoCs. The sensors capture noise at a fine granularity and store the SoC's critical status bits. The sensor network has been designed in 28/32nm standard cell library and its performance is demonstrated in the physical design of Open SPARCT1 multicore processor SoC