A Coherent and Power-Efficient Optical Memory Access Network for Kilo-Core Processor
2019
Coherent and power-efficient processor-memory interconnects are of great importance for kilo-core processor design. This paper proposes a hybrid photonic architecture for such interconnection. Specifically, a bandwidth-efficient photonic network which also supports coherence management is used for memory accesses between last-level HBM caches and off-chip HMC memory pools. Simulation results show that the hybrid network achieves up to 11% of system speedup and up to 6 times of energy savings, when compared to conventional electric interconnects.
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