FPGA Design for Efficient Architecture for the Convolution Encoder and Viterbi Decoder

Convolution encoding is used in almost all digital communication systems to get better gain BER and all applications need high throughput rate. The main aim of this paper is to design FPGA based convolution encoder and viterbi decoder which encodes/decodes the data. In this paper we are presenting an efficient design structure for the convolution encoder and decoder (Viterbi) for the FPGA implementation we also analyzed the developed mode for noisy situations for it correcting capabilities. The proposed model is synthesized and simulated using Xilinx ISE 14.4 software which shows that the proposed design effectively reduces the resource requirements and the power analysis on X-Power Analyzer shows considerable reduction in power requirements.