Lithography aware design optimization using ILT

For increasingly small and dense designs requiring adequate DOF, MEEF, and EL, numerous technologies have been employed to increase yield. Some techniques such as process optimization (i.e. SMO) are effective, but can be costly and time consuming, and are not easily modifiable once an initial choice is made. Design optimization can be done separately from knowledge of the fab's OPC correction, but for sub 32nm nodes the complexity and interaction of the design target shapes is becoming too complicated for predefined design rules to produce an acceptable result. In this paper we introduce a method called Lithographically Enhanced Edge Design (LEED) suited for IDMs. This joint target and mask optimization method takes into account the full OPC correction and process, and modifies the user's design in a controlled way so as to produce a new design with improved lithographic performance which can be used in place of the initial design. Control is given to the user so that inter-layer dependencies are not broken. Also, integrated target, mask, and source optimization is available in cases where target and mask optimization in not sufficient to produce adequate results. The use of ILT allows efficient target, mask, and source correction without extensive user OPC scripting and target modification sweeping. We show LEED results which enable production at 20x node.