Impacts of Operation Intervals on Program Disturb in 3D Charge-trapping Triple-level-cell (TLC) NAND Flash Memory

To evaluate the impacts of operation intervals on reliability properties in 3D charge-trapping (CT) NAND flash memory, systematical characterizations on raw NAND chips are performed with different intervals between program and erase (P/E) cycling. By focusing on the raw bit error rate (RBER) from cells' threshold voltage (V th ) shifts, it is found that the intervals in Program/Erase cycling have stronger impacts on the error modes than the degradation of total RBER. Larger intervals cause more error bits from V th up-shift and suppress error bits from V th down-shift, which can be explained by the impacts of lateral charge migration (LCM). These results are important to guide the design of error correcting code (ECC) in 3D NAND-based memory systems.