Design and Realisation of a Parallel Systolic Architecture Dedicated to Aerial Image Matching.

This paper addresses a hardware design of low cost, real time (faster than video rate) and suitable for on board applications systolic VLSI circuit, named pPD, for aerial image matching. Matching operation temporal results from Pentium PC200 (software simulation of the pPD) and estimated with Xilinx XC 6264 (encompassing pPD) working at 50 MHz are provided : the speed up factor is 2000 with frequency equivalent systems.