An 8t reconfigurable SrAm in 65-nm CmOS Achieving 0.25-1.2V Operating Voltage r

In modern integrated circuits (ICs), the trend of integrating more on-chip memories on a die has led SRAMs to account for a large fraction of total chip area as well as the total chip energy. Hence, applying energysaving schemes such as dynamic voltage scalability (DVS) to SRAMs is an important research area. However, optimizing circuit operation over a large voltage range is not trivial due to conflicting trade-offs of low-voltage (moderate and weak inversion) and high-voltage (strong inversion) transistor characteristics. Specifically, lowvoltage operation requires various assist circuits for functionality, which might severely impact high-voltage performance. Previous work in literature focused on either sub-threshold operation [1] or DVS in only the above-threshold regime [2]. In this work [3], SRAM design for a very large voltage range including both subthreshold and above-threshold regions is investigated. Reconfigurable circuit assists are proposed as a solution to the problem of optimizing circuits over a large voltage range with minimum performance penalty and power overhead.