Design of an ASIC architecture for high speed fractal image compression

We report the results of the design and performance evaluation of an ASIC dedicated to fractal image compression. The ASIC is to be hosted on a PC platform by means of an interface board connected to the PCI bus. The obtained speed-up is 300 times with respect to the direct execution of the compression algorithm on a 100 MHz Pentium platform. The ASIC has been synthesized from VHDL and totals 150000 transistors.