Understanding the Difference in Soft-Error Sensitivity of Back-Biased Thin-BOX SOI SRAMs to Space and Terrestrial Radiation

High tolerance against soft errors is regarded as one of the advantages of silicon-on-insulator (SOI) technology, as well as the reduction in power consumption by applying a back-bias from under the buried oxide layer (BOX). These advantages are appealing to Internet-of-Things (IoT) and space applications. Recently, it was found in a heavy-ion experiment that a static random-access memory (SRAM) fabricated with a 65-nm thin-BOX SOI technology exhibited a 100-fold soft-error sensitivity when it received a back-bias. This was due to long line-type formations of multiple cell upsets (MCUs) caused by radiation-induced potential perturbation under the BOX. However, devices fabricated with a similar technology tested with terrestrial neutrons did not show such a phenomenon in another previous study. To understand this difference, in the present work, a resistance-based model is adopted. Prediction of device soft-error sensitivity due to line-type MCUs under different radiation environment are also made. Then, characteristics of secondary ions generated by terrestrial neutrons in silicon devices are studied using simulation.