Efficient Hardware Implementation of the Fast Hybrid Morphological Reconstruction Algorithm

This work presents a hardware implementation of the morphological reconstruction algorithm for biomedical image analysis. The morphological reconstruction algorithm is based on the Fast Hybrid Reconstruction (FH). In this case, a hardware architecture has been developed and implemented by mapping the FH algorithm into a Cyclone V SoCKit-FPGA based platform, including an ARM processor. The developed architecture has been described in VHDL language, and it is scalable for image sizes of up to $512\times 512$ pixels using a neighboring element of $3\times 3$. The developed architecture can be replicated in order to allow the parallel processing of large images divided into blocks (one block being processed by an architecture module). Several results are presented comparing software, HW/SW co-design, and hardware implementations.