A Methodology for Measuri Gate-Drain Capacitance of CM

dn this paper, the author presents a new methodology for measuring the gate drain capacitance of CMOS devices using an accelerated dc measurement scheme. The gate-drain capac- itance was measured using a floating gate MOS transistor, i.e. an MOS transistor with an additional capacitor placed in series with the gate oxide capacitance. This structure was implemented transistors. The top capacitance couples charge onto the gate oxide capacitor and the gate-drain capacitor. The amount of coupling is determined by the ratio of these two capacitors. structure is measured; (iii) the s