Temperature-aware binding for clock skew reduction based on switching activity balancing

Recently, various physical level issues are considered in advance at the stage of high-level synthesis to save cost and get better performance or lower power. Among the issues, temperature variation is widely studied, but to the best of our knowledge, the bus binding method in high-level synthesis to consider clock skew distortion due to non-uniform distribution of temperature has not been proposed. In this paper, we propose binding method to aim at reducing clock skew by balancing switching activity of bus binding, and hence, by making the distribution of temperature uniform. Experimental result shows that the proposed method obtains binding solutions having 36.5–63.5% lower variance of switching activities among all bus groups in comparison to the existing binding method that does not consider the effect of temperature variation. Consequently, our heuristic binding method effectively reduces clock skew by 19.6–46.0% for seven benchmark circuits.