Top-down delayering to expose large inspection area on die side-edge with Platinum (Pt) deposition technique

Abstract The shrinking in feature sizes of semiconductor devices from integrated circuit (IC) 1 and function complexity has led to greater PFA 2 delayering challenges. The challenges stem from incorporation of top thick hard Silicon Dioxide (SiO 2 ) material that is formed from Tetra Ethyl Ortho Silicate (TEOS) 3 as Inter-Metal Dielectric (IMD) 4 and very thin ultra low-k dielectric material. For a device in copper (Cu) metal line technology, it is almost impossible to expose the entire layer at the same surface flatness by using a conventional top down polishing method, especially at the interface on TEOS and ultra low-k layer where die's side-edge is always thinner than die center (edging effect). Hence, for cases that required PFA delayering on the die side-edge especially for those packaged device or skeleton die, it is extremely challenging for PFA skillset. This paper outlines a proposed technique; perform Platinum (Pt) deposition on the selective area to slow down the side-edging effect. This proposed technique is easy and less skillset dependent to deprocess sample for defect identification analysis.