Approximate Decision Tree-Based Multiple Classifier Systems

Implementing hardware accelerators of multiple classifier systems assures an improving in performance: on one hand, the combination of multiple classifiers outcomes is able to improve classification accuracy, with respect to a single classifier; on the other hand, implementing the prediction algorithm by means of an integrated circuit enables classifier systems with higher throughput and better latency compared with a pure software architecture. Although, this approach requires a very high amount of hardware resources, limiting the adoption of commercial configurable devices, such as Field Programmable Gate Arrays. In this paper, we exploit the application of Approximate Computing to trade classification accuracy off for hardware resources occupation. Specifically, we adopt the bit-width reduction technique on a multiple classifier system based on the Random Forest approach. A case study demonstrates the feasibility of the methodology, showing an area reduction ranging between 8.3 and 72.3%.