Dynamic Partial Reconfiguration by Means of Algorithmic Skeletons—A Case Study

A digital hardware system which implementation does not fit in a FPGA device can be placed into the FPGA. The system with inherent parallelism must be partitioned into hardware modules to be executed in different time slots using partial reconfiguration. That is the so called temporal partitioning and temporal placement. The partitioning of the system can be done using standard patterns used in parallel systems. Algorithmic skeletons are common parallelization patterns which encapsulate parallelism, communication and synchronization. They help to avoid concentrating in unnecessary details about the underlying implementation of parallelism. Algorithmic skeletons seem to be promising as a methodology for the design of partial reconfigurable systems. In this chapter, the design of a speech recognition front-end is described to show the feasibility of using algorithmic skeletons in the design of reconfigurable systems. A speech recognition front-end is a digital signal processing device used to transform an audio signal into feature vectors used for Automatic Speech Recognition or storage of semantic audio information. This device does not fit in the fabric of the FPGA of the used development board. After it was redesigned using a developed library of algorithmic skeletons, the use of dynamic partial reconfiguration has made possible to fit the device into the FPGA. This chapter demonstrates how algorithmic skeletons allow to simplify and to speed up the development of partial reconfigurable systems.