PACT: Power Aware Compilation and Architectural Techniques

Abstract : The goal of this project was to take DoD applications written in C and generate power and performance efficient code for systems utilizing the architectural power-aware techniques developed. The PACT project consisted of 3 research tasks: 1) Power-aware architectural approaches, 2) Power-aware compilation strategies, and 3) Power-aware CAD tools for power estimation and synthesis. As part of the power aware architecture research, we developed power aware techniques for on-chip buses, power aware memory hierarchies, and a framework to evaluate heterogeneous embedded systems for performance and energy consumption. As part of the power aware compiler research, we have developed a compiler that takes general C programs and generates power aware codes for three targets: 1) General purpose embedded processor such as the StrongARM, 2) General purpose field-programmable gate arrays (FPGAs), and 3) General purpose application specific integrated circuits (ASICs). We have developed improved strategies for power optimization and management, and improved design methodologies and design philosophies for better estimation and optimization.