Effects of package design on top PoP package warpage

In recent years, Package on Package (PoP), in which a top memory packaging system is connected to a bottom logic package via solder joint, is a System-in-Package (SiP) solution adopted by more and more component manufacturers. To guarantee the yield and reliability of the solder joint between the top package and bottom package, mechanical compliance between these two packages is crucial during package stacking. Therefore package warpage needs to be understood and controlled to meet certain target. Due to the complexity of mechanical structures with multi dies and material behaviors of substrate, molding compound and die attach film, package design to meet specific and tight warpage requirement is very challenging, especially when the packaging technology is developed by an envelope approach. Design parameters including substrate design property, die stacking configuration, and package size of the top SiP package play very important role in warpage performance. In this paper, the effects of various packaging design parameters on warpage are studied through comprehensive experiment, modeling and simulation. The findings and results provide some clues and guideline for design for warpage, which can reduce the product's time to market (TTM).